Interrupt Source Register (Ecr) - Renesas NU85E Preliminary User's Manual

Caution When interrupt servicing is performed and control is returned by the RETI instruction after bit 0
of the EIPC, FEPC, or CTPC had been set (1) by the LDSR instruction, bit 0 is ignored (because bit
0 of the PC is fixed at 0). When setting a value in EIPC, FEPC, or CTPC, set an even value (bit 0 =
0) as long as there is no specific reason not to.
31
ECR
Bit Position Bit Name
31 to 16 FECC
15 to 0 EICC
56
CHAPTER 3 CPU
Figure 3-3. Interrupt Source Register (ECR)
16 15
FECC
Exception code of non-maskable interrupt (NMI) (See Table 8-1 Interrupt/Exception List.)
Exception code of exception or maskable interrupt (See Table 8-1 Interrupt/Exception List.)
Preliminary User's Manual A14874EJ3V0UM
EICC
Function
0
After reset
00000000H