Dtc Source Address Register (Sar); Dtc Destination Address Register (Dar) - Renesas H8SX/1650 Hardware Manual

7.2.3

DTC Source Address Register (SAR)

SAR is a 32-bit register that designates the source address of data to be transferred by the DTC.
In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR
are valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of
bit 23.
If a word or longword access is performed while an odd address is specified in SAR or if a
longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided
into multiple cycles to transfer data. For details, see section 7.5.1, Bus Cycle Division.
SAR cannot be accessed directly from the CPU.
7.2.4

DTC Destination Address Register (DAR)

DAR is a 32-bit register that designates the destination address of data to be transferred by the
DTC.
In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR
are valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of
bit 23.
If a word or longword access is performed while an odd address is specified in DAR or if a
longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided
into multiple cycles to transfer data. For details, see section 7.5.1, Bus Cycle Division.
DAR cannot be accessed directly from the CPU.
Section 7 Data Transfer Controller (DTC)
Rev.2.00 Jun. 28, 2007 Page 223 of 666
REJ09B0311-0200