Dma Source Address Register (Dsar) - Renesas H8SX/1520 Series Hardware Manual

Channel 3
• DMA source address register_3 (DSAR_3)
• DMA destination address register_3 (DDAR_3)
• DMA offset register_3 (DOFR_3)
• DMA transfer count register_3 (DTCR_3)
• DMA block size register_3 (DBSR_3)
• DMA mode control register_3 (DMDR_3)
• DMA address control register_3 (DACR_3)
• DMA module request select register_3 (DMRSR_3)
7.2.1

DMA Source Address Register (DSAR)

DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR
updates the transfer source address every time data is transferred. When DDAR is specified as the
destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored.
Although DSAR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
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31 30 29
0 0 0
R/W R/W R/W
23 22 21
0 0 0
R/W R/W R/W
15 14 13
0 0 0
R/W R/W R/W
7 6 5
0 0 0
R/W R/W R/W
Section 7 DMA Controller (DMAC)
28 27 26
0 0 0
R/W R/W R/W
20 19 18
0 0 0
R/W R/W R/W
12 11 10
0 0 0
R/W R/W R/W
4 3 2
0 0 0
R/W R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 137 of 804
25 24
0 0
R/W R/W
17 16
0 0
R/W R/W
9 8
0 0
R/W R/W
1 0
0 0
R/W R/W
REJ09B0104-0300