Slave Address Register (Sar) - Renesas H8S/2100 Series Hardware Manual

18.3.2

Slave Address Register (SAR)

SAR sets the slave address and selects the communication format. If the LSI is in slave mode with
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the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Bit Bit Name
7 SVA6
6 SVA5
5 SVA4
4 SVA3
3 SVA2
2 SVA1
1 SVA0
0 FS
Initial
Value R/W Description
0 R/W Slave Address 6 to 0
0 R/W Set a slave address.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W Format Select
Selects the communication format together with the
FSX bit in SARX. See table 18.3.
This bit should be set to 0 when general call address
recognition is performed.
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Section 18 I C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 537 of 994
REJ09B0452-0100