Figure 15.1 Block Diagram Of Lpc - Renesas H8S/2111B Hardware Manual

Figure 15.1 shows a block diagram of the LPC.
TWR0MW
TWR1–15
Cycle detection
Serial → parallel conversion
LAD0 to
LAD3
Serial ← parallel conversion
SYNC output
TWR0SW
TWR1–15
[Legend]
HICR0 to HICR3: Host interface control registers 0 to 3
LADR3H, 3L:
IDR1 to IDR3:
ODR1 to DOR3: Output data registers 1 to 3
STR1 to STR3:
Rev. 1.00, 05/04, page 368 of 544
Module data bus
IDR3
IDR2
IDR1
Address match
H'0060/64
H'0062/66
LADR3
ODR3
ODR2
ODR1
STR3
STR2
STR1
LPC channel 3 address register 3H and 3L
Input data registers 1 to 3
Status registers 1 to 3

Figure 15.1 Block Diagram of LPC

Parallel → serial conversion
SIRQCR0
SIRQCR1
Control logic
HISEL
LSCIE
LSCIB
LSCI input
LSMIE
LSMIB
LSMI input
PMEE
PMEB
PME input
HICR0
HICR1
HICR2
HICR3
Internal interrupt
control
TWR0MW:
TWR0SW:
TWR1 to TWR15: Two-way data registers 1 to 15
SERIRQ0, 1:
HISEL:
SERIRQ
CLKRUN
LPCPD
LFRAME
LRESET
LCLK
PB1 I/O LSCI
LSMI
PB0 I/O
PME
P80 I/O
GA20
IBFI1
IBFI2
IBFI3
ERRI
Two-way register 0MW
Two-way register 0SW
SERIEQ control registers 0 and 1
Host interface select register