Table 29.10 Timing Of On-Chip Peripheral Modules (1) - Renesas H8S/2158 User Manual

Section 29 Electrical Characteristics

Table 29.10 Timing of On-Chip Peripheral Modules (1)

Condition A: V = 3.0 V to 3.6 V, V
CC
Condition B: V = 2.7 V to 3.6 V, V
CC
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
FRT Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse
width
TMR Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock pulse
width
PWM, Pulse output delay time
PWMX
SCI Input clock cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D Trigger input setup time
converter
RESO output delay time
WDT
RESO output pulse width
Note: * Only the on-chip peripheral modules that can be used in subclock operation.
Rev. 3.00 Jan 25, 2006 page 846 of 872
REJ09B0286-0300
= 0 V, φ = 32.768 kHz * , 5 MHz to 25 MHz
SS
= 0 V, φ = 32.768 kHz * , 5 MHz to 20 MHz
SS
Symbol
t
PWD
t
PRS
t
PRH
t
FTOD
t
FTIS
t
FTCS
Single edge t
FTCWH
Both edges t
FTCWL
t
TMOD
t
TMRS
t
TMCS
Single edge t
TMCWH
Both edges t
TMCWL
t
PWOD
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
t
RESD
t
RESOW
Condition A Condition B
Min Max Min
— 40 —
30 — 40
30 — 40
— 40 —
30 — 40
30 — 40
1.5 — 1.5
2.5 — 2.5
— 40 —
30 — 40
30 — 40
1.5 — 1.5
2.5 — 2.5
— 40 —
4 — 4
6 — 6
0.4 0.6 0.4
— 1.5 —
— 1.5 —
— 40 —
30 — 40
30 — 40
30 — 40
— 200 —
132 — 132
Test
Max Unit Conditions
50 ns Figure 29.15
—
—
50 ns Figure 29.16
—
— Figure 29.17
— t
cyc
—
50 ns Figure 29.18
— Figure 29.20
— Figure 29.19
— t
cyc
—
50 ns Figure 29.21
— t Figure 29.22
cyc
—
0.6 t
Scyc
1.5 t
cyc
1.5
50 ns Figure 29.23
—
—
— ns Figure 29.24
200 ns Figure 29.25
— t
cyc