Bit Rate Register (Brr); Table 16.2 Relationships Between N Setting In Brr And Bit Rate B - Renesas H8S/2158 User Manual

16.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 16.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.

Table 16.2 Relationships between N Setting in BRR and Bit Rate B

Mode Bit Rate
Asynchronous
B =
mode
Clocked
B =
synchronous
mode
Smart card
B =
interface mode
Notes: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following table.
SMR Setting
CKS1
0
0
1
1
Table 16.3 shows sample N settings in BRR in normal asynchronous mode. Table 16.4 shows the
maximum bit rate settable for each frequency. Table 16.6 shows sample N settings in BRR in
clocked synchronous mode, and table 16.8 shows sample N settings in BRR in smart card
interface mode. In smart card interface mode, the number of basic clock cycles S in a 1-bit data
transfer time can be selected. For details, see section 16.7.4, Receive Data Sampling Timing and
Reception Margin. Tables 16.5 and 16.7 show the maximum bit rates with external clock input.
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
φ × 10
6
64 × 2 × (N + 1)
2n – 1
φ × 10
6
8 × 2 × (N + 1)
2n – 1
φ × 10
6
S × 2 × (N + 1)
2n + 1
CKS0 n
0 0
1 1
0 2
1 3
Error
{
Error (%) =
B × 64 × 2
—
{
Error (%) =
B × S × 2
SMR Setting
BCP1
0
0
1
1
Rev. 3.00 Jan 25, 2006 page 405 of 872
φ × 10
6
}
– 1 × 100
× (N + 1)
2n – 1
φ × 10
6
}
– 1 × 100
× (N + 1)
2n + 1
BCP0 S
0 32
1 64
0 372
1 256
REJ09B0286-0300