Register Bits - Renesas H8S/2158 User Manual

Item
17.7 Usage Notes
18.3.1 USB Data
FIFO
Table 18.2 FIFO
Configuration
25.4.1 TAP
Controller State
Transitions
Figure 25.2 TAP
Controller State
Transitions
28.1 Register
Addresses (Address
Order)

28.1 Register Bits

Page Revision (See Manual for Details)
551 (b) Set the MST bit to 1.
(c) To confirm that the bus was not entered to the busy state
while the MST bit is being set, check that the BBSY flag in the
ICCR register is 0 immediately after the MST bit has been set.
Note: Above restriction can be cleared by setting bits FNC1 and
FNC0 in the ICXR register.
557 Table 18.2 amended
Endpoint
Endpoint 4 EP4
Endpoint 5 EP5
755 Figure 25.2 replaced
792 Table amended
Register Name
Command register 5
Com mand start register
Operation control register
793 Table amended
Register Name
Response register 16
Response register D
Data timeout register H
804 Table amended
Register
Abbreviation Bit 7
CMDR5 CRC
CMDSTRT —
OPCR CMDOFF
805 Table amended
Register
Abbreviation Bit 7
RSPR16 Bit 7
PSPRD Bit 7
DTOUTRH DTOUT15 DTOUT14 DTOUT13 DTOUT12 DTOUT11 DTOUT10 DTOUT9
Transfer Direction FIFO Size
IN Max. 2048 bytes
OUT Max. 2048 bytes
Number
Abbreviation of Bits
CMDR5 8
CMDSTRT 8
OPCR 8
Number
Abbreviation of Bits
RSPR16 8
RSPRD 8
DTOUTRH 8
Bit 6 Bit 5 Bit 4 Bit 3
CRC CRC CRC CRC
— — — —
— RD_CONTI DATAEN —
Bit 6 Bit 5 Bit 4 Bit 3
Bit 6 Bit 5 Bit 4 Bit 3
Bit 6 Bit 5 Bit 4 Bit 3
Rev. 3.00 Jan 25, 2006 page xv of lii
Configuration Description
Max. 64 bytes RAM-FIFO
× 32 (RFU)
Max. 64 bytes
× 32
Number
Data of
Bus Access
Address Module Width States
H'FBC5 MCIF 8 3
H'FBC6 MCIF 8 3
H'FBCA MCIF 8 3
Number
Data of
Bus Access
Address Module Width States
H'FBF0 MCIF 8 3
H'FBF1 MCIF 8 3
H'FBF2 MCIF 8 3
Bit 2 Bit 1 Bit 0 Module
CRC CRC En d
MCIF
— — START
— — —
Bit 2 Bit 1 Bit 0 Module
Bit 2 Bit 1 Bit 0 MCIF
Bit 2 Bit 1 Bit 0
DTOUT8