Table of Contents
Advertisement
11.5
Operation
A PWM waveform like the one shown in figure 11.2 is output from the PWMX pin. The value in
DADR corresponds to the total width (T
(256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly
output. When OS = 1, the output waveform is inverted, and the DADR value corresponds to the
total width (T
) of the high (1) output pulses. Figures 11.3 and 11.4 show the types of waveform
H
output available.
t
f
Base cycle
(T × 64 or T × 256)
t
L
Table 11.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the
resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR
contains at least a certain minimum value.
) of the low (0) pulses output in one conversion cycle
L
1 conversion cycle
(T × 2
14
(= 16384))
Figure 11.2 PWM (D/A) Operation
Section 11 14-Bit PWM Timer (PWMX)
T: Resolution
m
= Σ t
T
(OS = 0)
L
Ln
n = 1
(When CFS = 0, m = 256
When CFS = 1, m = 64)
Rev. 3.00 Jan 25, 2006 page 281 of 872
REJ09B0286-0300
Advertisement
Table of Contents
