Timing Of On-Chip Supporting Modules - Renesas H8S/2633 Series Hardware Manual

25.3.5

Timing of On-Chip Supporting Modules

Table 25-9 lists the timing of on-chip supporting modules.
Table 25-9 Timing of On-Chip Supporting Modules
Condition A: V = PLLV
CC
V = 3.6 V to AV
ref
2 to 16 MHz, T
(wide-range specifications)
Condition B: V = PLLV
CC
V = 4.5 V to AV
ref
2 to 25 MHz, T
(wide-range specifications)
Item
I/O port Output data delay
time
Input data setup
time
Input data hold
time
PPG Pulse output delay
time
TPU Timer output
delay time
Timer input setup
time
Timer clock input
setup time
Timer
clock
pulse
width
1038
= 3.0 V to 3.6 V, PV
CC
* 2
, V = AV
CC SS
= –20°C to +75°C (regular specifications), T
a
= 3.0 V to 3.6 V, PV
CC
, V = AV
CC SS
= –20°C to +75°C (regular specifications), T
a
Symbol
t
PWD
t
PRS
t
PRH
t
POD
t
TOCD
t
TICS
t
TCKS
Single t
TCKWH
edge
Both t
TCKWL
edges
= 3.0 V to 5.5 V, AV
CC
= 0 V, ø = 32.768 kHz *
= PLLV
SS SS
= 4.5 V to 5.5 V, AV
CC
= PLLV = 0 V, ø = 32.768 kHz*
SS SS
Condition A Condition B
Min Max Min
— 60 —
40 — 25
40 — 25
— 60 —
— 60 —
40 — 25
40 — 25
1.5 — 1.5
2.5 — 2.5
= 3.6 V to 5.5 V *
CC
3
,
= –40°C to +85°C
a
= 4.5 V to 5.5 V,
CC
3
,
= –40°C to +85°C
a
Max Unit Test Conditions
40 ns Figure 25-20
—
—
40 ns Figure 25-21
40 ns Figure 25-22
—
— ns Figure 25-23
— t
cyc
—
1
,