Figure 17.1 Block Diagram Of I - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
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φ
SCL
SDA
1. ICDRX write = ICDRT write
Notes:
2. ICDRX read = ICDRR read
Legend:
2
ICCR
:
I
C bus control register
2
I
C bus mode register
ICMR
:
I
2
C bus status register
ICSR
:
I
2
C bus data register
ICDR
:
Slave address register
SAR
:
SARX
:
Second slave address register
IIC operation reservation adapter count register
ICCNT
:
IIC operation reservation adapter control register
ICCRX
:
IIC operation reservation adapter command register
ICCMD
:

Figure 17.1 Block Diagram of I

Timeout
decision
circuit
Command
control
PS
Clock
control
Noise
canceler
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
conrol
circuit
Noise
canceler
Section 17 I
Adapter
ICCNT
ICCRX
ICCMD
ICSRA
ICSRB
ICSRC
ICCR
ICMR
ICSR
ICDRX(W)
ICDRT
ICDRS
ICDRX(R)
ICDRR
Address comparator
SAR, SARX
Interrupt
generator
ICSRA
:
IIC operation reservation adapter status register A
ICSRB
:
IIC operation reservation adapter status register B
ICSRC
:
IIC operation reservation adapter status register C
ICDRX
:
IIC operation reservation adapter data register
ICDRT
:
IIC data transmit buffer
ICDRS
:
IIC data shift register
ICDRR
:
IIC data receive buffer
PS
:
Prescaler
2
C Bus Interface
Rev. 3.00 Jan 25, 2006 page 475 of 872
2
C Bus Interface (IIC)
*
1
*
2
Interrupt
request
REJ09B0286-0300

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