Renesas H8S/2158 User Manual page 45

Figure 21.2 D/A Converter Operation Example ...................................................................... 694
Section 22 A/D Converter
Figure 22.1 Block Diagram of A/D Converter......................................................................... 698
Figure 22.2 A/D Conversion Timing ....................................................................................... 707
Figure 22.3 External Trigger Input Timing.............................................................................. 708
Figure 22.4 A/D Conversion Accuracy Definitions ................................................................. 710
Figure 22.5 A/D Conversion Accuracy Definitions ................................................................. 710
Figure 22.6 Example of Analog Input Circuit.......................................................................... 711
Figure 22.7 Example of Analog Input Protection Circuit ........................................................ 713
Figure 22.8 Analog Input Pin Equivalent Circuit..................................................................... 713
Section 24 ROM
Figure 24.1 Block Diagram of Flash Memory ......................................................................... 718
Figure 24.2 Flash Memory State Transitions ........................................................................... 719
Figure 24.3 Boot Mode ............................................................................................................ 720
Figure 24.4 User Program Mode (Example) ............................................................................ 721
Figure 24.5 Flash Memory Block Configuration .................................................................... 722
Figure 24.6 On-Chip RAM Area in Boot Mode ...................................................................... 731
Figure 24.7 ID Code Area........................................................................................................ 731
Figure 24.8 Programming/Erasing Flowchart Example in User Program Mode ..................... 732
Figure 24.9 Program/Program-Verify Flowchart ..................................................................... 734
Figure 24.10 Erase/Erase-Verify Flowchart............................................................................... 736
Figure 24.11 Memory Map in Programmer Mode ..................................................................... 739
Section 25 User Debug Interface (H-UDI)
Figure 25.1 Block Diagram of H-UDI ..................................................................................... 742
Figure 25.2 TAP Controller State Transitions.......................................................................... 755
Figure 25.3 Reset Signal Circuit Without Reset Signal Interference ....................................... 758
Figure 25.4 Serial Data Input/Output (1) ................................................................................. 759
Figure 25.4 Serial Data Input/Output (2) ................................................................................. 760
Section 26 Clock Pulse Generator
Figure 26.1 Block Diagram of Clock Pulse Generator............................................................. 761
Figure 26.2 Typical Connection to Crystal Resonator ............................................................. 762
Figure 26.3 Equivalent Circuit of Crystal Resonator ............................................................... 762
Figure 26.4 Example of External Clock Input ......................................................................... 763
Figure 26.5 External Clock Input Timing ................................................................................ 764
Figure 26.6 Timing of External Clock Output Stabilization Delay Time ................................ 765
Figure 26.7 Subclock Input Timing ......................................................................................... 767
Figure 26.8 Note on Board Design of Oscillation Circuit Section........................................... 768
Rev. 3.00 Jan 25, 2006 page xliii of lii