Renesas H8S/2158 User Manual page 702

Section 19 Multimedia Card Interface (MCIF)
INTCR1
Bit Bit Name
7 INTRQ2E
6 INTRQ1E
5 INTRQ0E
4, 3 —
2 CRCERIE
1 DTERIE
0 CTERIE
Rev. 3.00 Jan 25, 2006 page 648 of 872
REJ09B0286-0300
Initial Value R/W
0 R/W
0 R/W
0 R/W
All 0 R
0 R/W
0 R/W
0 R/W
Description
Source 2 Interrupt Enable
0: Disables MCIF2 interrupt to the CPU.
1: Enables MCIF2 interrupt to the CPU.
Source 1 Interrupt Enable
0: Disables MCIF1 interrupt to the CPU.
1: Enables MCIF1 interrupt to the CPU.
Source 0 Interrupt Enable
0: Disables MCIF0 interrupt to the CPU.
1: Enables MCIF0 interrupt to the CPU.
Reserved
These bits are always read as 0 and cannot be
modified.
CRC Error Interrupt Enable
When this bit is set to 1 while the INTRQ2E bit
is 1, the CRC error interrupt request is enabled.
Data Timeout Error Interrupt Enable
When this bit is set to 1 while the INTRQ2E bit
is 1, the data timeout error interrupt request is
enabled.
Command Timeout Error Interrupt Enable
When this bit is set to 1 while the INTRQ2E bit
is 1, the command timeout error interrupt
request is enabled.