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8.8
Operation
The RFU is presupposed to operate with the following procedure:
• Enable ID to be written to the RFU, and store data received by the peripheral module into
FIFO.
• Enable ID to be read from the RAM-FIFO, and supply data transmitted by the peripheral
module from FIFO.
Two IDs can be enabled simultaneously. However, when OVER-READ or OVER-WRITE error
status occurs, sufficient error processing may not be made. Thus, the processing should be made
with a sufficient number of valid data bytes and free area bytes.
When the CPU reads and uses the received data, the read start address of the pointer status and the
number of valid data bytes are used. When the CPU generates data to be transmitted, data is
written to on-chip RAM, and then the RAM address where data is stored in the pointer is written.
8.8.1
Transmission/Reception of Single Data Block
To transmit a single data block or to receive a data block with a known number of bytes, boundary
overflow is convenient. Even if the peripheral module does not include a function to generate an
interrupt at the completion of the specified number of bytes of transfer data, the completion of data
block transmission/reception can be acknowledged by an interrupt from the RFU side. This
interrupt is generated when the RFU pointer reaches the boundary of the FIFO size specified by
bits BUD2 to BUD0 in DTCRA.
Table 8.6 summarizes the settings when boundary overflow is used.
Section 8 RAM-FIFO Unit (RFU)
Rev. 3.00 Jan 25, 2006 page 191 of 872
REJ09B0286-0300
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