Sleep Mode; Software Standby Mode; Figure 27.2 Medium-Speed Mode Timing - Renesas H8S/2158 User Manual

Section 27 Power-Down Modes
φ,
peripheral module clock
Bus master clock
Internal address bus
Internal write signal
27.4

Sleep Mode

The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the peripheral modules do not stop. The contents of the CPU's internal
registers are retained.
Sleep mode is exited by any interrupt, the RES pin, or the STBY pin.
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode
is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU.
Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation
stabilization time has passed, driving the RES pin high causes the CPU to start reset exception
handling.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
27.5

Software Standby Mode

The CPU makes a transition to software standby mode when the SLEEP instruction is executed
while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS
bit in TCSR (WDT_1) is cleared to 0.
In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all
stop. However, the contents of the CPU's internal registers, on-chip RAM data, I/O ports, and the
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SBYCR

Figure 27.2 Medium-Speed Mode Timing

Medium-speed mode
SBYCR