Slave Address Register (Sar) - Renesas H8S/2158 User Manual

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Section 17 I C Bus Interface (IIC)
17.3.2

Slave Address Register (SAR)

SAR sets the slave address and selects the communication format. When the LSI is in slave mode
with the addressing format selected, if the upper 7 bits of SAR match the upper 7 bits of the first
frame received after a start condition, the LSI operates as the slave device specified by the master
device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0.
Bit Bit Name Initial Value R/W
7 SVA6 0
6 SVA5 0
5 SVA4 0
4 SVA3 0
3 SVA2 0
2 SVA1 0
1 SVA0 0
0 FS 0
Rev. 3.00 Jan 25, 2006 page 480 of 872
REJ09B0286-0300
Description
R/W Slave Address 6 to 0
R/W Set a slave address.
R/W
R/W
R/W
R/W
R/W
R/W Format Select
Selects the communication format together with the FSX
bit in SARX. For details, see table 17.2. This bit should
be cleared to 0 when general call address recognition is
performed.