Pwm (D/A) Control Register (Dacr) - Renesas H8S/2158 User Manual

DADRB
Bit Bit Name Initial Value
15 DA13 1
14 DA12 1
13 DA11 1
12 DA10 1
11 DA9 1
10 DA8 1
9 DA7 1
8 DA6 1
7 DA5 1
6 DA4 1
5 DA3 1
4 DA2 1
3 DA1 1
2 DA0 1
1 CFS 1
0 REGS 1
11.3.3

PWM (D/A) Control Register (DACR)

DACR selects test mode, enables the PWM outputs, and selects the output phase and operating
speed.
R/W Description
R/W D/A Data 13 to 0
R/W
These bits set a digital value to be converted to an
R/W
analog value.
R/W
In each base cycle, the DACNT value is continually
R/W
compared with the DADR value to determine the duty
R/W
cycle of the output waveform, and to decide whether to
R/W
output a fine-adjustment pulse equal in width to the
R/W
resolution. To enable this operation, this register must
R/W
be set within a range that depends on the CFS bit. If the
R/W
DADR value is outside this range, the PWM output is
R/W
held constant.
R/W
R/W
A channel can be operated with 12-bit precision by
R/W
keeping both the DA0 and DA1 bits cleared to 0. This 2-
bit data is not compared with the UC12 and UC13 bits
in DACNT.
R/W Carrier Frequency Select
0: Base cycle = Resolution (T) × 64
Range of values in DA13 to DA0 = H'0100 to H'3FFF
1: Base cycle = Resolution (T) × 256
Range of values in DA13 to DA0 = H'0040 to H'3FFF
R/W Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. This bit specifies which
registers can be accessed. Make this bit setting before
changing the address register.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Section 11 14-Bit PWM Timer (PWMX)
Rev. 3.00 Jan 25, 2006 page 277 of 872
REJ09B0286-0300