Figure 11.4 Output Waveform (Os = 1, Dadr Corresponds To T H ); Figure 11.5 D/A Data Register Configuration When Cfs = 1 - Renesas H8S/2158 User Manual

Section 11 14-Bit PWM Timer (PWMX)
t
f1
t
H1
t = t
f1 f2
t + t
H1 H2
t
f1
t
H1
t = t
f1 f2
t + t
H1
Figure 11.4 Output Waveform (OS = 1, DADR corresponds to T
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWMX output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6)
in DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 11.5.
Table 11.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
Duty cycle of base pulse

Figure 11.5 D/A Data Register Configuration when CFS = 1

Rev. 3.00 Jan 25, 2006 page 284 of 872
REJ09B0286-0300
1 conversion cycle
t
f2
t
H2
= t = ··· = t = t = T× 64
f3 f255 f256
+ t + ··· + t + t = T
H3 H255 H256
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
t
f2
t
H2
= t = ··· = t = t = T× 256
f3 f63 f64
+ t + ··· + t + t = T
H2 H3 H63 H64
b. CFS = 1 [base cycle = resolution (T) × 256]
DA8 DA7
t
f255
t t
H3 H255
H
t
f63
t t
H3 H63
H
DA6 DA5 DA4 DA3
Location of additional pulses
t
f256
t
H256
t
f64
t
H64
)
H
DA2 DA1 DA0 CFS
1 1