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Section 8 RAM-FIFO Unit (RFU)
8.11
Usage Notes
1. Conflict between CPU write to DTRSR and RFU activation request
If conflict occurs between a CPU write to the RS bit in DTRSR while it is 0 and an RFU
activation request, data transfer by the RFU cannot be performed correctly.
In order to access the FIFO state, the RS bit must be set to 1 at RFU initialization in advance.
When the RS bit is cleared to 0, the CPU should not write to DTRSR during RFU data
processing.
2. FIFO full and FIFO empty states
When using a temporary pointer, the FIFO full and FIFO empty states during RFU data
processing cannot be retained successfully, and overread or overwrite of data may occur.
If making use of a temporary pointer, be sure to check on the number of bytes of valid data and
free area for the FIFO, and the EMPTY and FULL flag states before data processing.
3. DATAN/FREEN read value
If DATAN or FREEN is read in the FIFO full or FIFO empty state when the conditions listed
in table 8.7 are satisfied, the read values may not be correct. When DATAN or FREEN is read
as 0, whether the FIFO is full or empty needs to be checked by using the FULL and EMPTY
bits in DTSTRC.
Table 8.7
DATAN/FREEN Read Value
Pointer Mode
Write temporary
pointer
Read temporary
pointer
Temporary pointer
not used
4. RFU operation in medium-speed mode
This LSI does not support medium-speed mode operation of the RFU. When using the RFU in
medium-speed mode, the DTSPEED bit in SBYCR must be set to 1. If the RFU is activated
with the DTSPEED bit cleared to 0, the program may get out of control.
Rev. 3.00 Jan 25, 2006 page 204 of 872
REJ09B0286-0300
Condition
Write until the FIFO is full and request
a mark (when TMP = RAR)
Read until the FIFO is empty (when
WAR = RAR)
Write until the FIFO is full (when WAR
= RAR)
Read until the FIFO is empty and
request a mark (when TMP = WAR)
Write until the FIFO is full
Read until the FIFO is empty
DATAN/FREEN Read Value
DATAN = 0 even though the
FIFO is full
FREEN = 0 even though the
FIFO is empty
DATAN = 0 even though the
FIFO is full
FREEN = 0 even though the
FIFO is empty
DATAN = 0 even though the
FIFO is full
FREEN = 0 even though the
FIFO is empty
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