Renesas H8S/2158 User Manual page 522

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
CRC Control Register (CRCCR): CRCCR initializes the CRC operation circuit, switches the
operation mode, and selects the generating polynomial.
Bit Bit Name
7 DORCLR
6 to 3 —
2 LMS
1 G1
0 G0
CRC Data Input Register (CRCDIR): CRCDIR is an 8-bit readable/writable register, to which
the bytes to be CRC-operated are written. The result is obtained in CRCDOR.
CRC Data Output Register (CRCDOR): CRCDOR is a 16-bit readable/writable register that
contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR
after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to
which CRC operation is to be performed, the CRC operation result will be H'0000 if the data
contains no CRC error. When bits 1 and 0 in CRCCR (G1 and G0 bits) are set to 0 and 1,
respectively, the lower byte of this register contains the result.
Rev. 3.00 Jan 25, 2006 page 468 of 872
REJ09B0286-0300
Initial Value R/W
0 W
All 0 R
0 R/W
0 R/W
0
R/W
Description
CRCDOR Clear
Setting this bit to 1 clears CRCDOR to H'0000.
Reserved
The initial value should not be changed.
CRC Operation Switch
Selects CRC code generation for LSB-first or
MSB-first communication.
0: Performs CRC operation for LSB-first
communication. The lower byte (bits 7 to 0) is
first transmitted when CRCDOR contents
(CRC code) are divided into two bytes to be
transmitted in two parts.
1: Performs CRC operation for MSB-first
communication. The upper byte (bits 15 to 8)
is first transmitted when CRCDOR contents
(CRC code) are divided into two bytes to be
transmitted in two parts.
CRC Generating Polynomial Select:
Selects the polynomial.
00: Reserved
8 2
01: X + X + X + 1
16 15 2
10: X + X + X + 1
16 12 5
11: X + X + X + 1