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Section 29 Electrical Characteristics
2
Table 29.11 I
C Bus Timing
Condition A: V
= 3.0 V to 3.6 V, V
CC
Condition B: V
= 2.7 V to 3.6 V, V
CC
Item
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA output fall time
SCL, SDA input spike pulse
elimination time
SDA input bus free time
Start condition input hold time
Retransmission start
condition input setup time
Stop condition input setup
time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Note:
* 17.5 t
can be set according to the clock selected for use by the IIC module.
cyc
Rev. 3.00 Jan 25, 2006 page 850 of 872
REJ09B0286-0300
= 0 V, φ = 5 MHz to 25 MHz
SS
= 0 V, φ = 5 MHz to 20 MHz
SS
Symbol
Min
Typ
t
12
—
SCL
t
3
—
SCLH
t
5
—
SCLL
t
—
—
Sr
t
—
—
Sf
t
20 +
—
Of
0.1 Cb
t
—
—
SP
t
5
—
BUF
t
3
—
STAH
t
3
—
STAS
t
3
—
STOS
t
0.5
—
SDAS
t
0
—
SDAH
C
—
—
b
Max
Unit
Test Conditions
—
t
Figure 29.26
cyc
—
—
7.5 *
300
ns
250
1
—
t
cyc
—
—
—
—
—
ns
400
pF
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