Input/Output Pins - Renesas H8S/2158 User Manual

6.2

Input/Output Pins

Table 6.1 summarizes the pins of the bus controller.
Table 6.1 Pin Configuration
Symbol I/O
AS
Output
IOS
Output
CPCS1, CPCS2
Output
CS256
Output
RD/CPOE
Output
HWR/CPWE
Output
LWR
Output
WAIT/CPWAIT
Input
Function
Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output (the 256-kbyte expansion
area is accessed while the CS256E bit in SYSCR is 1) or
when the CP/CF expansion area is accessed (the CPCSE bit
in BCR2 is 1).
I/O select signal (when the IOSE bit in SYSCR is set to 1).
Chip select signal indicating that the CP/CF expansion area is
being accessed (in mode 2 or when the CPCSE bit in BCR2
is set to 1).
Chip select signal indicating that the 256-kbyte expansion
area is being accessed (in mode 2 or when the CS256E bit in
SYSCR is set to 1).
Strobe signal indicating that the external address space is
being read.
Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8) of the data
bus is enabled.
(Note however that the effective data bus must be specified
by the CPCS1 and CPCS2 signals when the CP/CF
expansion area is being accessed.)
Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0) of the data bus
is enabled.
Wait request signal when accessing the external 3-state
access space or CP/CF expansion area.
Rev. 3.00 Jan 25, 2006 page 105 of 872
Section 6 Bus Controller
REJ09B0286-0300