Figure 22.2 A/D Conversion Timing; Table 22.4 A/D Conversion Time (Single Mode) - Renesas H8S/2158 User Manual

φ
Address
Write signal
Input sampling
timing
ADF
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
t : A/D conversion start delay
D
t : Input sampling time
SPL
t : A/D conversion time
CONV

Table 22.4 A/D Conversion Time (Single Mode)

Item
A/D conversion start delay
time
Input sampling time
A/D conversion time
Note: Values in the table indicate the number of states.
(1)
(2)
t t
D SPL

Figure 22.2 A/D Conversion Timing

Symbol min
t 10
D
t —
SPL
t 259
CONV
Section 22 A/D Converter
t
CONV
CKS = 0
typ max
— 17
63 —
— 266
Rev. 3.00 Jan 25, 2006 page 707 of 872
CKS = 1
min typ max
6 — 9
— 31 —
131 — 134
REJ09B0286-0300