Figure 24.27 Dmac Dreq Input Timing; Table 24.10 Timing Of On-Chip Peripheral Modules - Renesas H8S/2368 Series Hardware Manual

,
(5) Timing of On-Chip Peripheral Modules

Table 24.10 Timing of On-Chip Peripheral Modules

Conditions: V = 3.0 V to 3.6 V, AV
CC
φ = 8 MHz to 33 MHz, T
T = –40°C to +85°C (wide-range specifications)
a
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
PPG Pulse output delay time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time t
Timer clock
pulse width
8-bit timer Timer output delay time
Timer reset input setup time t
Timer clock input setup time t
Timer clock
pulse width
Rev. 2.00, 05/03, page 762 of 820
Figure 24.27 DMAC DREQ
= 3.0 V to 3.6 V, V
CC
= –20°C to +75°C (regular specifications),
a
Symbol Min
t
PWD
t
PRS
t
PRH
t
POD
t
TOCD
t
TICS
TCKS
Single-edge t
TCKWH
specification
Both-edge t
TCKWL
specification
t
TMOD
TMRS
TMCS
Single-edge t
TMCWH
specification
Both-edge t
TMCWL
specification
t t
DRQS DRQH
DREQ Input Timing
DREQ DREQ
= 3.0 V to AV
ref
Max
— 40
25 —
25 —
— 40
— 40
25 —
25 —
1.5 —
2.5 —
— 40
25 —
25 —
1.5 —
2.5 —
, V = AV = 0 V,
CC SS SS
Unit Test Conditions
ns Figure 24.28
ns
ns
ns Figure 24.29
ns Figure 24.30
ns
ns Figure 24.31
t
cyc
t
cyc
ns Figure 24.32
ns Figure 24.34
ns Figure 24.33
t
cyc
t
cyc