Figure 16.34 Clock Output Fixing Timing - Renesas H8S/2158 User Manual

CKE0
SCK
At power-on and transitions to/from software standby mode, use the following procedure to secure
the appropriate clock duty ratio.
At Power-On:
To secure the appropriate clock duty ratio simultaneously with power-on, use the following
procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
pull-up or pull-down resistor.
2. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
3. Set SMR and SCMR to enable smart card interface mode.
4. Set the CKE0 bit in SCR to 1 to start clock output.
At Transition from Smart Card Interface Mode to Software Standby Mode:
1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK
pins to the values for the output fixed state in software standby mode.
2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the
CKE1 bit to the value for the output fixed state in software standby mode.
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the
specified level with the duty ratio retained.
5. Make the transition to software standby mode.
At Transition from Software Standby Mode to Smart Card Interface Mode:
1. Cancel software standby mode.
2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty
ratio is then generated.
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Specified pulse width

Figure 16.34 Clock Output Fixing Timing

Specified pulse width
Rev. 3.00 Jan 25, 2006 page 455 of 872
REJ09B0286-0300