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3.3.2
Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The
CPU can access a 56-kbyte address space in mode 3.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
In extended mode, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an
address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions
as a data bus, and parts of port 9 carry bus control signals. Port 6 functions as a data bus when the
ABW bit in WSCR is cleared to 0.
3.3.3
Pin Functions
Pin functions of ports 1 to 3, 6, 9, and A depend on the operating mode. Table 3.2 shows pin
functions in each operating mode.
Table 3.2
Pin Functions in Each Operating Mode
Port
Port 1
Port 2
Port 3
Port 6
Port 9
P97
P96
P95 to P93
P90
Port A
Legend:
*: After reset
Mode 2
I/O port * /Address bus output
I/O port * /Address bus output
I/O port * /Data bus I/O
I/O port * /Data bus I/O
I/O port * /Control signal output
Input port * /Clock I/O
I/O port * /Control signal output
I/O port * /Control signal output
I/O port * /Address bus output
Section 3 MCU Operating Modes
Mode 3
I/O port * /Address bus output
I/O port * /Address bus output
I/O port * /Data bus output
I/O port * /Data bus output
I/O port * /Control signal output
Input port * /Clock I/O
I/O port * /Control signal output
I/O port * /Control signal output
I/O port *
Rev. 3.00 Jan 25, 2006 page 61 of 872
REJ09B0286-0300
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