Table 8.4 Requests From Peripheral Modules And Rfu Bus Cycle - Renesas H8S/2158 User Manual

Section 8 RAM-FIFO Unit (RFU)
Table 8.4 Requests from Peripheral Modules and RFU Bus Cycle
Requests from
Transfer Condition and FIFO Pointer
Peripheral
Modules Status
RAM → peripheral
Data transfer
modules
TMP is not used
RAM → peripheral
modules
TMP is used as
a read temporary
pointer
Peripheral modules
→ RAM
TMP is not used
Peripheral modules
→ RAM
TMP is used as
a write temporary
pointer
Rev. 3.00 Jan 25, 2006 page 186 of 872
REJ09B0286-0300
RFU Bus Cycle
Contents
Other than RAM read, peripheral
the following module write cycle
RAR = WAR after RAM read, peripheral
RAR addition module write cycle
Notification of FIFO
empty state
RAR = WAR Notification of FIFO
overread state
Other than RAM read, peripheral
the following module write cycle
RAR = WAR after RAM read, peripheral
RAR addition module write cycle
Notification of FIFO
empty state
RAR = WAR Notification of FIFO
overread state
Other than RAM read, peripheral
the following module write cycle
WAR = RAR after Peripheral module read,
WAR addition RAM write cycle
Notification of FIFO
full state
WAR = RAR Notification of FIFO
overwrite state
Other than RAM read, peripheral
the following module write cycle
WAR = RAR after Peripheral module read,
WAR addition RAM write cycle
Notification of FIFO full
state
WAR = RAR Notification of FIFO
overwrite state
Pointer
Manipulation
Adds RAR
Adds RAR
No pointer
manipulations
Adds RAR
Adds RAR
No pointer
manipulations
Adds WAR
Adds WAR
No pointer
manipulations
Adds WAR
Adds WAR
No pointer
manipulations