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Selecting devices whose input timing permits this output timing for use as slave devices
connected to the I
2
Table 17.13 I
C Bus Timing (with Maximum Influence of t
t
cyc
Item
Indication
t
0.5 t
(–t
)
Standard mode
SCLHO
SCLO
Sr
High-speed mode
t
0.5 t
(–t
)
Standard mode
SCLLO
SCLO
Sf
High-speed mode
t
0.5 t
– 1 t
Standard mode
BUFO
SCLO
cyc
( –t
)
Sr
High-speed mode
t
0.5 t
– 1 t
Standard mode
STAHO
SCLO
cyc
(–t
)
Sf
High-speed mode
t
1 t
(–t
)
Standard mode
STASO
SCLO
Sr
High-speed mode
t
0.5 t
+ 2 t
Standard mode
STOSO
SCLO
cyc
(–t
)
Sr
High-speed mode
*
3
t
1 t
– 3
Standard mode
SDASO
SCLLO
(master)
t
cyc
High-speed mode
(–t
)
Sr
*
3
t
1 t
–
Standard mode
SDASO
SCLL
*
2
(slave)
3 t
cyc
High-speed mode
(–t
)
Sr
t
3 t
Standard mode
SDAHO
cyc
High-speed mode
Notes:
1. Does not meet the I
necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by
means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave
devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits CKS2 to
CKS0. Depending on the frequency it may not be possible to achieve the maximum transfer rate;
therefore, whether or not the I
accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
3. Calculated using the I
1300 ns min.).
2
C bus.
Time Indication (at Maximum Transfer Rate) [ns]
2
I
C Bus
t
/t
Specifi-
Sr
Sf
Influence
cation
(Max.)
(Min.)
–1000
4000
–300
600
–250
4700
–250
1300
–1000
4700
–300
1300
–250
4000
–250
600
–1000
4700
–300
600
–1000
4000
–300
600
–1000
250
–300
100
–1000
250
–300
100
0
0
0
0
2
C bus interface specifications. Remedial action such as the following is
2
C bus interface specifications are met must be determined in
2
C bus specification values (standard mode: 4700 ns min.; high-speed mode:
Section 17 I
/t
)
Sr
Sf
φ φ φ φ =
φ φ φ φ =
φ φ φ φ =
5 MHz
8 MHz
10 MHz
4000
4000
4000
950
950
950
4750
4750
4750
1000 *
1
1000 *
1
1000 *
1
3800 *
3875 *
3900 *
1
1
1
850 *
750 *
825 *
1
1
1
4550
4625
4650
800
875
900
9000
9000
9000
2200
2200
2200
4400
4250
4200
1350
1200
1150
3100
3325
3400
400
625
700
1300
2200
2500
–1400 *
1
–500 *
1
–200 *
1
600
375
300
600
375
300
Rev. 3.00 Jan 25, 2006 page 543 of 872
2
C Bus Interface (IIC)
φ φ φ φ =
φ φ φ φ =
φ φ φ φ =
16 MHz
20 MHz
25 MHz
4000
4000
4000
950
950
950
4750
4750
4750
1000 *
1
1000 *
1
1000 *
3938 *
3950 *
3960 *
1
1
888 *
900 *
910 *
1
1
4688
4700
4710
938
950
960
9000
9000
9000
2200
2200
2200
4125
4100
4080
1075
1050
1030
3513
3550
3580
813
850
880
2950
3100
3220
250
400
520
188
150
120
188
150
120
– 6 t
).
SCLL
cyc
REJ09B0286-0300
1
1
1
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