24.4
Input/Output Pins
The flash memory is controlled by means of the pins shown in table 24.2.
Table 24.2 Pin Configuration
Pin Name
I/O
RES
Input
MD2
Input
MD1
Input
MD0
Input
FWE
Input
TxD1
Output
RxD1
Input
24.5
Register Descriptions
The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2,
the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the
serial/timer control register, see section 3.2.3, Serial Timer Control Register (STCR).
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
24.5.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode,
program-verify mode, erase mode, or erase-verify mode. For details on register setting, see section
24.8, Flash Memory Programming/Erasing.
FLMCR1 is initialized to H'00 by a reset, or in hardware standby mode, software standby mode,
sub-active mode, sub-sleep mode, or watch mode.
Function
Reset
Sets this LSI's operating mode
Sets this LSI's operating mode
Sets this LSI's operating mode
Flash memory pin
Serial transmit data output
Serial receive data input
Rev. 3.00 Jan 25, 2006 page 723 of 872
Section 24 ROM
REJ09B0286-0300