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Section 20 Electrical Characteristics
20.3.4
Timing of On-Chip Peripheral Modules
Table 20.7 Timing of On-Chip Peripheral Modules
Conditions: V
= 3.0 V to 3.6 V, AV
CC
V
= AV
SS
T
= –20°C to +75°C (regular specifications),
a
T
= –40°C to +85°C (wide-range specifications)
a
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
TPU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
PPG
Pulse output delay time
8-bit
Timer output delay time
timer
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
WDT
Overflow output delay time
SCI
Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Rev.2.00 Jun. 28, 2007 Page 640 of 666
REJ09B0311-0200
= 3.0 V to 3.6 V, V
CC
= 0 V, Pφ = 8 MHz to 35 MHz,
SS
Symbol
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
Single-edge
t
TCKWH
setting
Both-edge
t
TCKWL
setting
t
POD
t
TMOD
t
TMRS
t
TMCS
Single-edge
t
TMCWH
setting
Both-edge
t
TMCWL
setting
t
WOVD
Asynchronous
t
Scyc
Clocked
synchronous
t
SCKW
t
SCKr
t
SCKf
= 3.0 V to AV
ref
Min.
Max.
Unit
40
ns
25
ns
25
ns
40
ns
25
ns
25
ns
1.5
t
cyc
2.5
t
cyc
40
ns
40
ns
25
ns
25
ns
1.5
t
cyc
2.5
t
cyc
40
ns
4
t
cyc
6
0.4
0.6
t
Scyc
1.5
t
cyc
1.5
t
cyc
,
CC
Test Conditions
Figure 20.21
Figure 20.22
Figure 20.23
Figure 20.24
Figure 20.25
Figure 20.26
Figure 20.27
Figure 20.28
Figure 20.29
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