Renesas H8S/2158 User Manual page 916

Appendix
MCU
Port Name Operating
Pin Name Mode
Port 7 2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
Port 8 2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
Port 97 2, 3 (EXPE = 1)
WAIT,
CPWAIT,
CS256
2, 3 (EXPE = 0)
Port 96 2, 3 (EXPE = 1)
φ, EXCL
2, 3 (EXPE = 0)
Port 95 to 93 2, 3 (EXPE = 1)
AS, IOS,
HWR, CPWE,
RD, CPOE
2, 3 (EXPE = 0)
Port 92, 91 2, 3 (EXPE = 1)
CPCS1,
CPCS2
2, 3 (EXPE = 0)
Port 90 2, 3 (EXPE = 1)
LWR
2, 3 (EXPE = 0)
Port A 2, 3 (EXPE = 1)
A17, A16
2, 3 (EXPE = 0)
Legend:
H: High level
L: Low level
T: High impedance
kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up
MOS remains on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR.
DDR: Data direction register
Note: * In the case of address output, the last address accessed is retained.
Rev. 3.00 Jan 25, 2006 page 862 of 872
REJ09B0286-0300
Hardware Software
Standby Standby
Reset Mode Mode
T T T
T T kept
T T T/kept
kept
T T [DDR = 1]
H
[DDR = 0]
T
T T H
kept
T T kept
T T H/kept
kept
kept *
T T
Watch Sleep Subsleep
Mode Mode Mode
T T T
kept kept kept
T/kept T/kept T/kept
kept kept kept
EXCL [DDR = EXCL
input 1] input
Clock
output
[DDR =
0]
T
H H H
kept kept kept
kept kept kept
H/kept H/kept H/kept
kept kept kept
kept * kept * kept *
Program
Subactive Execution
Mode State
Input port Input port
I/O port I/O port
WAIT/ WAIT/
CPWAIT/ CPWAIT/
CS256/ CS256/
I/O port I/O port
I/O port I/O port
EXCL input Clock output/
EXCL input/
Input port
AS/IOS, AS/IOS,
HWR/CPWE, HWR/CPWE,
RD/CPOE RD/CPOE
I/O port I/O port
CPCS1, CPCS1,
CPCS2/ CPCS2/
I/O port I/O port
I/O port I/O port
LWR/ LWR/
I/O port I/O port
I/O port I/O port
A17, A16/ A17, A16/
I/O port I/O port
I/O port I/O port