Table of Contents
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5.3.7
Wake-Up Event Interrupt Mask Register (WUEMR3) ........................................ 83
5.4
Interrupt Sources ............................................................................................................... 84
5.4.1
External Interrupts ............................................................................................... 84
5.4.2
Internal Interrupts................................................................................................. 86
5.5
Interrupt Exception Handling Vector Table...................................................................... 86
5.6
Interrupt Control Modes and Interrupt Operation ............................................................. 90
5.6.1
Interrupt Control Mode 0 ..................................................................................... 92
5.6.2
Interrupt Control Mode 1 ..................................................................................... 94
5.6.3
Interrupt Exception Handling Sequence .............................................................. 96
5.6.4
Interrupt Response Times .................................................................................... 98
5.6.5
DTC Activation by Interrupt................................................................................ 99
5.7
Usage Notes ...................................................................................................................... 101
5.7.1
Conflict between Interrupt Generation and Disabling ......................................... 101
5.7.2
Instructions that Disable Interrupts ...................................................................... 102
5.7.3
Interrupts during Execution of EEPMOV Instruction.......................................... 102
6.1
Features ............................................................................................................................. 103
6.2
Input/Output Pins .............................................................................................................. 105
6.3
Register Descriptions ........................................................................................................ 106
6.3.1
Bus Control Register (BCR) ................................................................................ 106
6.3.2
Bus Control Register 2 (BCR2) ........................................................................... 108
6.3.3
Wait State Control Register (WSCR) .................................................................. 110
6.3.4
Wait State Control Register 2 (WSCR2) ............................................................. 112
6.4
Bus Control ....................................................................................................................... 113
6.4.1
Bus Specifications................................................................................................ 113
6.4.2
Advanced Mode ................................................................................................... 121
6.4.3
Normal Mode....................................................................................................... 122
6.4.4
I/O Select Signals................................................................................................. 122
6.5
Basic Bus Interface ........................................................................................................... 123
6.5.1
Data Size and Data Alignment............................................................................. 123
6.5.2
Valid Strobes........................................................................................................ 124
6.5.3
Basic Operation Timing ....................................................................................... 125
6.5.4
Wait Control ........................................................................................................ 133
6.6
Burst ROM Interface......................................................................................................... 134
6.6.1
Basic Operation Timing ....................................................................................... 135
6.6.2
Wait Control ........................................................................................................ 136
6.7
Memory Card Interface ..................................................................................................... 137
6.7.1
Data Size and Data Alignment............................................................................. 137
6.7.2
Valid Strobes........................................................................................................ 138
.................................................................................................... 103
Rev. 3.00 Jan 25, 2006 page xix of lii
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