Renesas H8S/2158 User Manual page 28

Section 15 Watchdog Timer (WDT)
15.1 Features ............................................................................................................................. 373
15.2 Input/Output Pins .............................................................................................................. 375
15.3 Register Descriptions ........................................................................................................ 375
15.3.1 Timer Counter (TCNT)........................................................................................ 375
15.3.2 Timer Control/Status Register (TCSR) ................................................................ 376
15.4 Operation........................................................................................................................... 379
15.4.1 Watchdog Timer Mode ........................................................................................ 379
15.4.2 Interval Timer Mode ............................................................................................ 381
15.4.3 RESO Signal Output Timing ............................................................................... 382
15.5 Interrupt Sources ............................................................................................................... 382
15.6 Usage Notes ...................................................................................................................... 383
15.6.1 Notes on Register Access..................................................................................... 383
15.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 384
15.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 384
15.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 384
15.6.5 System Reset by RESO Signal............................................................................. 385
15.6.6 Counter Values during Transitions between High-Speed, Sub-Active,
and Watch Modes ................................................................................................ 385
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
16.1 Features ............................................................................................................................. 387
16.2 Input/Output Pins .............................................................................................................. 391
16.3 Register Descriptions ........................................................................................................ 391
16.3.1 Receive Shift Register (RSR) .............................................................................. 392
16.3.2 Receive Data Register (RDR) .............................................................................. 392
16.3.3 Transmit Data Register (TDR)............................................................................. 392
16.3.4 Transmit Shift Register (TSR) ............................................................................. 392
16.3.5 Serial Mode Register (SMR)................................................................................ 393
16.3.6 Serial Control Register (SCR).............................................................................. 396
16.3.7 Serial Status Register (SSR) ................................................................................ 398
16.3.8 Smart Card Mode Register (SCMR) .................................................................... 404
16.3.9 Bit Rate Register (BRR) ...................................................................................... 405
16.3.10 Serial Interface Control Register (SCICR)........................................................... 412
16.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2) .................... 412
16.3.12 Serial RFU Enable Register_0 and 2 (SCIDTER_0 and SCIDTER_2) ............... 416
16.4 Operation in Asynchronous Mode .................................................................................... 417
16.4.1 Data Transfer Format ........................................................................................... 418
16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 419
16.4.3 Clock.................................................................................................................... 420
16.4.4 Serial Enhanced Mode Clock............................................................................... 421
Rev. 3.00 Jan 25, 2006 page xxvi of lii
.............................................................................. 373
.................... 387