Usage Notes; Figure 25.3 Reset Signal Circuit Without Reset Signal Interference - Renesas H8S/2158 User Manual

Section 25 User Debug Interface (H-UDI)
25.6

Usage Notes

1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not
the H-UDI is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For
details, see section 29, Electrical Characteristics. To activate the H-UDI after a reset, drive the
ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the H-UDI is
not to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-
impedance state. These pins are internally pulled up and are noted in standby mode.
2. The following must be considered when the power-on reset signal is applied to the ETRST pin.
 The reset signal must be applied at power-on.
 To prevent the LSI system operation from being affected by the ETRST pin of the board
tester, circuits must be separated .
 Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI
system reset, circuits must be separated.
Figure 25.3 shows a design example of the reset signal circuit wherein no reset signal
interference occurs.
Board edge pin
System reset
ETRST

Figure 25.3 Reset Signal Circuit Without Reset Signal Interference

3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode,
IDCODE mode will be entered.
4. The frequency of the ETCK pin must be lower than that of the system clock. For details, see
section 29, Electrical Characteristics.
5. Data input/output in serial data transfer starts from the LSB. Figure 25.4 shows examples of
serial data input/output.
6. When data that exceeds the number of bits of the register connected between the ETDI and
ETDO pins is serially transferred, the serial data that exceeds the number of register bits and
output from the ETDO pin is the same as that input from the ETDI pin.
7. If the H-UDI serial transfer sequence is disrupted, the ETRST pin must be reset. Transfer
should then be retried, regardless of the transfer operation.
Rev. 3.00 Jan 25, 2006 page 758 of 872
REJ09B0286-0300
Power-on
reset circuit
This LSI
RES
ETRST