Figure 29.29 H-Udi Etck Timing; Table 29.14 H-Udi Timing - Renesas H8S/2158 User Manual

Section 29 Electrical Characteristics

Table 29.14 H-UDI Timing

Condition A: V = 3.0 V to 3.6 V, V
CC
Condition B: V = 2.7 V to 3.6 V, V
CC
Item
ETCK clock cycle time
ETCK clock high pulse width
ETCK clock low pulse width
ETCK clock rise time
ETCK clock fall time
ETRST pulse width
Reset hold transition pulse width
ETMS setup time
ETMS hold time
ETDI setup time
ETDI hold time
ETDO data delay time
≥ t
Note: * t
cyc TCKcyc
ETCK
Rev. 3.00 Jan 25, 2006 page 854 of 872
REJ09B0286-0300
= 0 V, φ = 5 MHz to 25 MHz
SS
= 0 V, φ = 5 MHz to 20 MHz
SS
Symbol Min
40 *
t
TCKcyc
t 15
TCKH
t 15
TCKL
t —
TCKr
t —
TCKf
t 20
TRSTW
t 10
RSTHW
t 20
TMSS
t 20
TMSH
t 20
TDIS
t 20
TDIH
t —
TDOD
t
TCKcyc
t t
TCKH TCKf

Figure 29.29 H-UDI ETCK Timing

Max Unit
500 *
ns
—
—
5
5
— t
cyc
—
— ns
—
—
—
20
t t
TCKL TCKr
Test Conditions
Figure 29.29
Figure 29.30
Figure 29.31