Wait Control; Figure 6.15 Access Timing Example In Burst Rom Space (Ast = Brsts1 = 0) - Renesas H8S/2158 User Manual

Section 6 Bus Controller
Full access Burst access
T T T T
1 2 1 1
φ
Only lower
Address bus address changes
AS/IOS
(IOSE = 0)
RD
Data bus
Read data Read data Read data

Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)

6.6.2

Wait Control

As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin
can be used in the initial cycle (full access) of the burst ROM interface. For details, see section
6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle.
Rev. 3.00 Jan 25, 2006 page 136 of 872
REJ09B0286-0300