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Section 28 Electrical Characteristics
28.3.3
Timing of On-Chip Peripheral Modules
Table 28.7 shows the on-chip peripheral module timing. The on-chip peripheral modules that can
be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to
IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer (WDT_1)
only. The system clock or LCLK operation can be used in the FSI.
Table 28.7 Timing of On-Chip Peripheral Modules
Conditions:
V
= 3.0 V to 3.6 V, V
CC
operating frequency, FSICK = 8 MHz to maximum operating frequency or LCLK
(33 MHz)
Item
I/O ports
Output data delay time*
Input data setup time
Input data hold time
TPU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
TMR
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
TCM
TCM input setup time
TCM clock input setup time
TCM clock pulse width
TDP
TDP input setup time
TDP clock input setup time
TDP clock pulse width
PWMU, PWMX
Pulse output delay time
SCI
Input clock cycle
Input clock pulse width
Rev. 1.00 Apr. 28, 2008 Page 968 of 994
REJ09B0452-0100
= 0 V, φ = 32.768 kHz*
SS
Symbol
2
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
Single edge
t
TCKWH
Both edges
t
TCKWL
t
TMOD
t
TMRS
t
TMCS
Single edge
t
TMCWH
Both edges
t
TMCWL
t
TCMS
t
TCMCKS
t
TCMCKW
t
TDPS
t
TDPCKS
t
TDPCKW
t
PWOD
Asynchronous
t
Scyc
Synchronous
t
SCKW
, φ = 8 MHz to maximum
1
Min.
Max.
Unit
50
ns
30
30
50
ns
30
30
1.5
t
cyc
2.5
50
ns
30
30
1.5
t
cyc
2.5
30
ns
30
1.5
t
cyc
30
ns
30
1.5
t
cyc
50
ns
4
t
cyc
6
0.4
0.6
t
Scyc
Test
Conditions
Figure 28.9
Figure 28.10
Figure 28.11
Figure 28.12
Figure 28.14
Figure 28.13
Figure 28.15
Figure 28.16
Figure 28.17
Figure 28.18
Figure 28.19
Figure 28.20
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