Input Capture Input Timing; Figure 12.7 Input Capture Input Signal Timing (Usual Case); Figure 12.8 Input Capture Input Signal Timing (When Icra To Icrd Is Read) - Renesas H8S/2158 User Manual

Section 12 16-Bit Free-Running Timer (FRT)
12.5.4

Input Capture Input Timing

The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 12.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
Input capture signal

Figure 12.7 Input Capture Input Signal Timing (Usual Case)

If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (φ). Figure 12.8 shows the timing for this case.
φ
Input capture
input pin
Input capture signal

Figure 12.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read)

Rev. 3.00 Jan 25, 2006 page 302 of 872
REJ09B0286-0300
Read cycle of ICRA to ICRD
T 1 T 2