Figure 6.10 Bus Timing For 16-Bit, 3-State Access Space (Even Byte Access) - Renesas H8S/2158 User Manual

Section 6 Bus Controller
16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Address bus
AS/IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1 and CFE = 0)
AS/IOS * (IOSE = 0)
Read
Write
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1.

Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)

Rev. 3.00 Jan 25, 2006 page 130 of 872
REJ09B0286-0300
T
1
φ
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Bus cycle
T T
2 3
High level
Valid
Undefined
Valid
Invalid