Renesas H8S/2158 User Manual page 107

BCLR instruction executed
BCLR #0,
After executing BCLR
P47
Input/output Output
Pin state Low
level
DDR 1
DR 1
[Description on Operation]
1. When the BCLR instruction is executed, first the CPU reads P4DDR.
Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a
value of H'3F, but the value read by the CPU is H'FF.
2. The CPU clears bit 0 of the read data to 0, changing data to H'FE.
3. The CPU writes H'FE to DDR, completing execution of BCLR.
As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin.
However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins.
The BCLR instruction is executed for DDR in port 4
@P4DDR
P46 P45
Output Output
High Low
level level
1 1
0 0
P44 P43 P42
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
Rev. 3.00 Jan 25, 2006 page 53 of 872
Section 2 CPU
P41 P40
Output Input
Low High
level level
1 0
0 0
REJ09B0286-0300