Table of Contents
Advertisement
Section 15 Watchdog Timer (WDT)
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer
can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing
to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset
signal or an internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT is shown in figure 15.1.
15.1
Features
• Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
•
If the counter overflows, an internal reset or an internal NMI interrupt is generated.
• When the LSI is selected to be internally reset at counter overflow, a low level signal is output
from the RESO pin if the counter overflows.
Internal Timer Mode:
•
If the counter overflows, an internal timer interrupt (WOVI) is generated.
WDT0102A_000020020300
Section 15 Watchdog Timer (WDT)
Rev. 3.00 Jan 25, 2006 page 373 of 872
REJ09B0286-0300
Advertisement
Table of Contents
