Addressing Modes And Effective Address Calculation; Figure 2.11 Instruction Formats (Examples) - Renesas H8S/2158 User Manual

Section 2 CPU
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
2.7

Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Rev. 3.00 Jan 25, 2006 page 44 of 872
REJ09B0286-0300
op
op
op
EA (disp)
op cc

Figure 2.11 Instruction Formats (Examples)

NOP, RTS
r m
r n
ADD.B Rn, Rm
r n r m
MOV.B @(d:16, Rn), Rm
EA (disp) BRA d:16