Endpoint Stall Register 0 (Epstlr0) - Renesas H8S/2158 User Manual

Section 18 Universal Serial Bus Interface (USB)
Bit Bit Name Initial Value R/W
0 — 0
Note: * Writing of 0 is disabled.

18.3.12 Endpoint Stall Register 0 (EPSTLR0)

EPSTLR0 stalls the USB function core endpoints. Endpoints whose EPSTL bits are set to 1
respond by a STALL handshake when a transaction has been initiated by receiving a token from
the host. A stall state (STALL handshake is used to respond) can be set from both the USB
function core and the host. A stall state can be cancelled only from the host. The stall state is
specified in the USB function core internal bit. This internal bit can be set or cleared by the
SetFeature/Clear Feature command of the host. If STALL handshaking is performed because the
EPSTL bit is set to 1, the internal bit of the USB function core is also set to a stall state. Even if
the host clears the USB function core internal bit, this internal bit remains to be set to a stall state
until the corresponding EPSTL bit is set to 1.
EPSTLR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16,
USB Control Registers 0 and 1 (USBCR0, USBCR1)).
EPSTLR0
Bit Bit Name Initial Value R/W
7 — 0
6 EP5STL 0
Rev. 3.00 Jan 25, 2006 page 584 of 872
REJ09B0286-0300
Description
R/(W) Reserved
The initial value should not be changed.
Description
R Reserved
This bit is always read as 0 and cannot be modified.
R/W Endpoint 5 Stall
Sets endpoint 5 in a stall state.
0: Endpoint 5 is in an operating state.
(Stall state can be cancelled by the ClearFeature
command)
[Clearing condition] (SCME = 1)
•
STALL handshake response of endpoint 5 is
performed.
1: Endpoint 5 is in a stall state.
[Clearing condition] (SCME = 1)
•
1 is written to EP5STL after EP5STL = 0 has been
read.