Renesas H8S/2158 User Manual page 236

Section 8 RAM-FIFO Unit (RFU)
Bit Bit Name
7 CHS2
6 CHS1
5 CHS0
4 RS
3 POS1
2 POS0
1 STS1
0 STS0
Rev. 3.00 Jan 25, 2006 page 182 of 872
REJ09B0286-0300
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Pointer Number Select
These bits represent the pointer set number to
be accessed from FSTR, DTCRA, DTCRB,
DTIDR, and DTSTRC.
Register Select
Selects whether to access register/pointer or
FIFO status by FSTR.
0: FSTR accesses register/pointer
1: FSTR accesses FIFO status
Register/Pointer Select 1, 0
These bits select the register/pointer to be
accessed by FSTR while the RS bit is 0.
00: The base address register (BAR) is
accessed by FSTR
01: The read address pointer (RAR) is
accessed by FSTR
10: The write address pointer (WAR) is
accessed by FSTR
11: The temporary pointer (TMP) is accessed
by FSTR
FIFO Status Selects 1, 0
These bits select the FIFO status to be
accessed by FSTR while the RS bit is 1.
00: The valid data byte number (DATATN) is
accessed by FSTR
01: The free area byte number (FREEN) is
accessed by FSTR
10: The read start address (NRA) is accessed
by FSTR
11: The write start address (NWA) is accessed
by FSTR
To access NWA, NRA, FREEN, or DATATN
while the RS bit is 0, write 1 to the RS bit twice.