Section 14 Timer Connection; Features - Renesas H8S/2158 User Manual

Section 14 Timer Connection

Section 14 Timer Connection
This LSI allows interconnection between a 16-bit free-running timer (FRT) and three 8-bit timer
channels (TMR_1, TMR_X, and TMR_Y). This capability can be used to implement complex
functions such as PWM decoding and clamp waveform output.
14.1

Features

• Five input pins and four output pins, all of which can be designated for phase inversion.
• Positive logic is assumed for all signals used within the timer connection facility.
• An edge-detection circuit is connected to the input pins, simplifying signal input detection.
• TMR_X can be used for PWM input signal decoding.
• TMR_X can be used for clamp waveform generation.
• An external clock signal divided by TMR_1 can be used as the FRT capture input signal.
• An internal synchronization signal can be generated using the FRT and TMR_Y.
• A signal generated/modified using an input signal and timer connection can be selected and
output.
Figure 14.1 shows a block diagram of the timer connection facility.
Rev. 3.00 Jan 25, 2006 page 345 of 872
TIMC0N01A_000020020300
REJ09B0286-0300