Usb Pll Control Register (Upllcr); Table 18.3 Port 6 Functions - Renesas H8S/2158 User Manual

Table 18.3 Port 6 Functions

Port 6
P67 (DPLS)
P66 (DMNS)
P65 (XVERDATA)
P64 (TXDPLS)
P63 (TXDMNS)
P62 (TXENL)
P61 (SUSPEND)
P60 (SPEED)

18.3.17 USB PLL Control Register (UPLLCR)

UPLLCR controls the generation method of the USB function core operating clock.
UPLLCR is initialized to H'01 by a system reset.
Control I/O of Driver/Receiver Compatible with PDIUSBP11A
by Philips Electronics
Input VP
Input VM
Input RCV
Output VPO
Output VMO
OE
Output
Output SUSPEND
Output SPEED
Section 18 Universal Serial Bus Interface (USB)
Differential input (+)
Differential input (–)
Data input
Differential input (+)
Differential input (–)
Output enable
Suspend specification
Speed specification (Fixed to high for
12-Mbps specifications)
Rev. 3.00 Jan 25, 2006 page 595 of 872
REJ09B0286-0300