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2
Section 17 I
C Bus Interface (IIC)
Bit
Bit Name
Initial Value R/W
1
IRIC
0
Rev. 3.00 Jan 25, 2006 page 488 of 872
REJ09B0286-0300
Description
R/(W) * I
2
C Bus Interface Interrupt Request Flag
Indicates that the IIC module has issued an interrupt
request to the CPU.
This flag is set at different times depending on the FS bit
in SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
For details, see section 17.5.6, IRIC Setting Timing and
SCL Control. The conditions under which this flag is set
also differ depending on the setting of the ACKE bit in
ICCR.
[Setting conditions]
2
I
C bus format master mode:
•
When a start condition is detected in the bus line
state after a start condition is issued (when the
ICDRE flag is set to 1 because of first frame
transmission)
•
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
•
At the end of data transfer (rise of the 9th
transmit/receive clock without no waits)
•
When a slave address is received after bus arbitration
is lost (first frame after start condition)
•
If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1) when the ACKE bit is 1
•
When the AL flag is set to 1 after bus arbitration is
lost while the ALIE bit is 1
2
I
C bus format slave mode:
•
When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1) and
at the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th transmit/receive clock)
•
When the general call address is detected (when 0 is
received as the R/W bit and the ADZ flag in ICSR is
set to 1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (rise of the 9th receive clock)
•
If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1) when the ACKE bit is 1
•
When a stop condition is detected (when the STOP or
ESTP flag in ICSR is set to 1) when the STOPIM bit is
0
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