Renesas H8S/2158 User Manual page 112

Section 3 MCU Operating Modes
Bit Bit Name Initial Value
2 NMIEG 0
1 KINWUE 0
0 RAME 1
Rev. 3.00 Jan 25, 2006 page 58 of 872
REJ09B0286-0300
R/W Description
R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
R/W Keyboard Control Register Access Enable
Enables or disables CPU access for input control
registers (KMIMRA, KMIMR6, WUEMR3) of KINn and
WUEn pins, input pull-up MOS control register
(KMPCR6) of the KINn pin, registers (TCR_X/TCR_Y,
TCSR_X/TCSR_Y, TICRR/TCORA_Y,
TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR,
TCORA_X, TCORB_X) of 8-bit timers (TMR_X,
TMR_Y), and timer connection registers (TCONRI,
TCONRO, TCONRS, SEDGR).
0: Enables CPU access for registers of TMR_X and
TMR_Y and timer connection registers in an area
from H'(FF)FFF0 to H'(FF)FFF7 and from
H'(FF)FFFC to H'(FF)FFFF.
1: Enables CPU access for input control registers of
the KINn and WUEn pins and the input pull-up MOS
control register of the KINn pin in an area from
H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to
H'(FF)FFFF.
R/W RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled