Iic Operation Reservation Adapter Status Register A (Icsra) - Renesas H8S/2158 User Manual

Bit Bit Name Initial Value
1 AASHIT 0
0 ACKBX 0
3 CLR3 —
2 CLR2 —
1 CLR1 —
0 CLR0 —
17.3.8

IIC Operation Reservation Adapter Status Register A (ICSRA)

ICSRA monitors the operating status of the IIC module.
Bit Bit Name Initial Value
7 SDAO 1
6 SCLO 1
5 SDAI —
4 SCLI —
R/W Description
R Slave Address Match
0: In master mode or slave address does not match
1: Slave address matches
R Acknowledge Bit Transmission Reserve
0: Reserves transmission of acknowledge bit 0
1: Reserves transmission of acknowledge bit 1
W Clear 3 to 0
W Writing B'0101 to these bits with an MOV instruction
initializes the internal latch circuit and state machine of
W
the conventional IIC module and the IIC operation
W
reservation adapter. The appropriate control bits of the
conventional IIC module and the IIC operation
reservation adapter must be initialized so as to
deactivate the IIC module.
When bits 7 to 4 in this register are set/cleared using a
bit manipulation instruction, the contents in BBSYX and
AASHIT are written to the CLR3 to CLR0 bits by
read/modify/write operation. However, since bit 2 is
always read as 0, clearing operation cannot be
executed.
R/W Description
R SDA Output Value
Monitors the output value from the SDA pin.
R SCL Output Value
Monitors the output value from the SCL pin.
R SDA Input Level
Monitors the input level to the SDA pin.
R SCL Input Level
Monitors the input level to the SCL pin.
2
Section 17 I C Bus Interface (IIC)
Rev. 3.00 Jan 25, 2006 page 497 of 872
REJ09B0286-0300