Section 8 Ram-Fifo Unit (Rfu); Features - Renesas H8S/2158 User Manual

Section 8 RAM-FIFO Unit (RFU)

This LSI incorporates a RAM-FIFO unit (RFU). The RFU is activated by a request from the
peripheral modules and can transfer data between the peripheral modules and on-chip RAM. As
the RFU can specify the RAM address to be transferred by using a pointer that is updated for
every data transfer execution, the RAM specified area can be regarded as an FIFO. If an FIFO
full/empty or overrun error occurs according to pointer update, the RFU can acknowledge this
error to the peripheral modules. The peripheral modules request pointer reset and manipulation of
the temporary pointer in addition to data transfer.
A block diagram of the RFU is shown in figure 8.1.
8.1

Features

• Bus master with priority higher than that of the CPU and DTC
• Provides the RFU-ID to specific peripheral modules (SCI, USB, and MCIF) to specify the
peripheral modules to be manipulated by the RFU with ID numbers
• RFU bus cycle accesses the peripheral modules and on-chip RAM simultaneously
• During an RFU bus cycle, the address bus outputs a RAM address for data transfer
• RAM address for data transfer is specified by the on-chip pointer set of the RFU
• Four pointer sets
• The contents of the pointer set are updated for every data transfer, and a specific RAM area
can be manipulated as the FIFO (RAM-FIFO)
• RAM-FIFO size: 32/64/128/256/512/1024/2048 bytes selectable
• An interrupt can be generated by a RAM-FIFO full/empty or overrun error
• RFU operates in high-speed mode even when the LSI is in medium-speed mode
RAMFU00A_000020020300
Section 8 RAM-FIFO Unit (RFU)
Rev. 3.00 Jan 25, 2006 page 167 of 872
REJ09B0286-0300